Conductive bump structure of circuit board and method for fabricating the same

ABSTRACT

A conductive bump structure of a circuit board and a method for fabricating the same are proposed. The circuit board with a plurality of electrical connection pads is provided. An insulating protective layer and a resist layer are successively applied on the circuit board, wherein openings are formed in the layers at positions corresponding to the pads to expose the pads. Then, a conductive layer is formed on surfaces of the resist layer and openings, and a metal layer is formed on the conductive layer via electroplating and filled in the openings. Subsequently, the metal layer and conductive layer formed on the resist layer are removed via thinning, so as to form metal bumps on the pads. After the resist layer is removed, the metal bumps are covered by an adhesive layer to form a conductive bump structure for electrically connecting the circuit board to the external electronic component.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims benefit under 35 USC 119 of Taiwan ApplicationNo. 094107081, filed on Mar. 9, 2005.

FIELD OF THE INVENTION

The present invention relates to conductive bump structures of circuitboards and methods for fabricating the same, and more particularly, to aconductive bump structure formed on an electrical connection pad of acircuit board for electrically connecting the circuit board to theexternal electronic component.

BACKGROUND OF THE INVENTION

The flip chip packaging technology was introduced by IBM in the early1960s, and this technology differs from the wire bonding technology inthat the electrical connectivity between the semiconductor chip and thesubstrate is achieved by the solder bumps instead of the ordinary wires.The main advantage of the flip chip packaging technology lies in itscapability of elevating packaging density, thus the size of the packagedcomponents are reduced; on the other hand, the flip chip packagingtechnology does not require wires of longer length, and hence theelectrical functionality can be improved. As a result, the industry hasbeen employing high-temperature soldering on ceramic substrates foryears, and this technology is termed as control-collapse chip connectionor 4C technology. Because the demand for semiconductor components ofhigh-density, high-speed, low-cost has increased dramatically, and atrend that calls for smaller electronic products has emerged; it hasbecome common to place the flip chip components on a low-cost organiccircuit board (for example, a printed circuit board or a substrateboard), then followed by the filling of epoxy underfill resin underneaththe chip in order to minimize the thermal stress resulted from thedifferences in thermal expansion between silicon chip and organiccircuit board structure, and the phenomenon has grown exponentially.

In the current flip chip packaging technology, the surface ofsemiconductor integrated circuit chip is disposed an electrode padthereof, and its corresponding connecting pads are disposed on theorganic circuit board; solder bumps or other conductive solder materialsare filled between the chip and the circuit board, so that the chip isdisposed on the circuit board with its electrical connecting side facingdownwards. The solder bumps or the conductive adhesive materials used inthis technology provides for the electrical input and output, as well asthe mechanical connection between the chip and the circuit board.

As shown in FIG. 1, in the flip chip packaging technology, a pluralityof metal bumps 11 are formed on electrode pads 12 of a chip 13, and aplurality of preset solder bumps 14 made of solder are formed onelectrical connection pads 15 of a circuit board 16, then solder joint17 are formed by reflowing preset solder bumps 14 to the correspondingmetal bumps 11 under the condition of having the temperature sufficientfor melting the preset solder bumps 14. In the next step, the chip andthe circuit board are coupled by using the underfill material 18, sothat the integration and the reliability of the electrical connectionbetween chip 13 and circuit board 16 can be ensured.

Moreover, when the circuit board and the semiconductor chip are to bepackaged, a plurality of solder balls are required to be implanted onthe bottom surface of the circuit board, so that it is possible for thecircuit board to electrically connect to external electronic devices. Inorder to allow the solder balls to connect to the circuit boardeffectively, the electrical connection pads of the circuit board thatare to be used for the disposition of solder balls must be formed withthe solder materials for connecting the solder balls first.

Currently, the method that is most commonly used to form solder materialon the electrical connection pad of the circuit board is the stencilprinting technology. As shown in FIG. 2, a solder-mask layer 21 isformed on a circuit board 20 that has been wired with circuits, then aplurality of electrical connection pads 22 are exposed, so that astencil 23 with a plurality of openings 23 a are placed on thesolder-mask layer 21 of the circuit board 20; solder deposition can beformed on the electrical connection pads 22 by the openings 23 a (notshown in the figure). A roller 24 or spray mode can be utilized to allowthe solder to accumulate in the openings 23 a, and once stencil 23 isremoved, the solder deposition is formed in the openings 23 a. This isfollowed by the reflowing process, which allows the solder deposition onthe electrical connection pads 22 to solidify into the solder structure.

However, the developmental trend of miniaturization for semiconductorchip is driving changes in the semiconductor packaging technology, inorder to allow the ever-shrinking chips to have more input and outputterminals. But the change also shrinks the total area of carriedcomponents in a chip, which in turn increases the quantity of electricalconnection pad on the carried components; as a result, the demands forthe development of chip can only be satisfied by shrinking the size andthe pitch of electrical connection pad. But the shrinking of electricalconnection pad also makes the openings on the stencil used in stencilprinting technology smaller as well. As a result, the smaller openingson the stencil not only increases the cost for producing the stencil,which is resulted from difficulty in stencil production; but alsohampers the later production process because the smaller opening on thestencil can be impervious to the solder material. Furthermore, apartfrom the requirement of accurate size of stencil in order to ensure theprecision in the shaping of solder material; there are the problems ofthe number of times the stencil has been used and cleaned. Since thesolder material is viscous, it can stick to the inner wall of openingsin the stencil and accumulate as the stencil is used to print manytimes, and this can give rise to incorrect quantity and shape of soldermaterial from the design specification when the stencil is used nexttime. Therefore, when the stencil is put to actual usage, it must becleaned after a certain times of printing, otherwise problems likeconflicting shape and size of solder material can arise and result inthe production process being impeded, which lowers its reliability.

To solve the above disadvantages, the method of electroplating has beenemployed to form solder material on the circuit board. FIGS. 3A to 3Dare figures showing the procedural steps in the method forelectroplating preset solder bumps on the circuit board. As shown inFIG. 3A, a solder mask layer 31 is formed on the circuit board 30 thathas electrical connection pads 300, then openings 310 are formed on thesolder mask layer 31 to expose the electrical connection pads 300 of thecircuit board 30. As shown in FIG. 3B, a conductive layer 32 is formedon the surface of solder mask layer 31 and its openings 310, then anelectroplated resist layer 33 that is to be electroplated and formedwith openings 330 is formed on the conductive layer 32, so that theconductive layer 32 covered on the electrical connection pads 300 isexposed. As shown in FIG. 3C, the electroplating process is carried out,which utilizes the conductivity of conductive layer 32 as theelectrically conductive pathway during electroplating, so that soldermaterial 34 is formed by electroplating in the openings 330 that are tobe electroplated. As shown in FIG. 3D, the resist layer 33 and theportion of the conductive layer 32 covered by the resist layer 33 areremoved, then followed by solder reflowing so that preset solder bumps35 are formed on the electrical connection pads of the circuit board.

Although the above procedures can solve the problems of stencil printingdescribed previously, the difficulty of electroplating can be increaseddue to minimal area for electroplating, because solder materials 34 isformed in the openings of resist layer by direct electroplating.Moreover, when solder material is formed on the electrical connectionpads in the openings of solder mask layer by direct electroplating, itbecomes difficult to control the height of solder material on theelectrical connection pads, which can lead to problems like unevenheight of conductive bumps on the surface of circuit board, and thiswill have serious impact on the reliability of the electrical connectingprocess of later circuit boards and external electronic components(especially semiconductor chips).

SUMMARY OF THE INVENTION

In light of the above prior art drawbacks, a primary objective of thepresent invention is to provide a conductive bump structure of thecircuit board and a method for fabricating the same to avoid problemsrelated to formation of conductive bumps of uneven height on a surfaceof the circuit board, so as to ensure the reliability of the subsequentelectrical connecting process for circuit boards and external electroniccomponents.

Another objective of the present invention is to provide a conductivebump structure of the circuit board and a method for fabricating thesame to avoid problems such as having the difficulty of electroplatingincreased due to minimal area for electroplating.

Still another objective of the present invention is to provide aconductive bump structure of the circuit board and a method forfabricating the same to reduce the amount of solder materials used andthe cost of production.

A further objective of the present invention is to provide a conductivebump structure of the circuit board and a method for fabricating thesame to effectively form conductive bumps serving as external electricalconnections on fine-pitch electrical connection pads of the circuitboard.

Yet another objective of the present invention is to provide aconductive bump structure of the circuit board and a method forfabricating the same to prevent restrictions on size of conductivebumps, an increase in production cost or complexity of fabricationprocess.

In accordance with the foregoing and other objectives, the presentinvention proposes a method for fabricating a conductive bump structureof the circuit board, comprising steps of: providing the circuit boardhaving at least a surface formed with a plurality of electricalconnection pads; forming an insulating protective layer and a resistlayer on the circuit board in sequence; forming a plurality of openingsin the insulating protective layer and resist layer at positionscorresponding to the electrical connection pads to expose the electricalconnection pads of the circuit board; forming a conductive layer onsurfaces of the resist layer and openings; forming a metal layer on theconductive layer via electroplating, and filling the metal layer in theopenings of the insulating protective layer and resist layer; removingthe metal layer and conductive layer formed on the surface of the resistlayer via thinning, and retaining the metal layer and conductive layerfilled in the openings to form metal bumps on the electrical connectionpads; and removing the resist layer via chemical etching or physicaltearing, and forming an adhesive layer over exposed surfaces of themetal bumps, so as to form the conductive bump structure forelectrically connecting the circuit board to the externalelectroniccomponent. Further, the metal layer may be made of a material selectedfrom the group consisting of copper (Cu), tin (Sn), lead (Pb), silver(Ag), and their alloys; the adhesive layer may be made of a materialselected from the group consisting of copper (Cu), tin (Sn), lead (Pb),silver (Ag), nickel (Ni), gold (Au), platinum (Pt) and their alloys, orbe an organic solderability preservative (OSP).

In another preferred embodiment, the present invention proposes a methodfor fabricating a conductive bump structure of the circuit board,comprising steps of: providing the circuit board having at least asurface formed with a plurality of electrical connection pads; formingan insulating protective layer on the circuit board in sequence, andforming a plurality of openings in the insulating protective layer toexpose the electrical connection pads of the circuit board; forming aresist layer on the insulating protective layer, and forming a pluralityof openings in the resist layer at positions corresponding to theopenings of the insulating protective layer to expose the electricalconnection pads; forming a conductive layer on exposed surfaces of theresist layer and openings; forming a metal layer on the conductive layervia electroplating, and filling the metal layer in the openings;removing the resist layer, the conductive layer and metal layer formedon the surface of the resist layer via chemical etching or physicaltearing so as to form metal bumps on the electrical connection pads ofthe circuit board, wherein the metal bumps comprise the metal layer andconductive layer; and forming an adhesive layer over exposed surfaces ofthe metal bumps. Furthermore, the insulating protective layer can bepreviously formed with a plurality of openings to expose the electricalconnection pads on the surface of the circuit board. Then, the resistlayer formed on the insulating protective layer with a plurality ofopenings located at positions corresponding to the electrical connectionpads. However, the insulating protective layer and resist layer may besuccessively formed first, before forming the openings of the insulatingprotective layer and resist layer at the same time.

Referring to the aforementioned fabricating methods, a conductive bumpstructure of the circuit board fabricated in accordance with presentinvention is provided, wherein a surface of the circuit board is formedwith an electrical connection pad and covered by an insulatingprotective layer, an opening is formed in the insulating protectivelayer to expose the electrical connection pad covered by the insulatingprotective layer and the conductive bump structure is formed on theelectrical connection pad of the circuit board and protruded from theopening of the insulating protective layer. Further, the conductive bumpstructure comprises a metal bump having a metal layer and a conductivelayer formed on the lateral and bottom sides of the metal layer, whereinthe metal bump is protruded from the opening of the insulating layer;and an adhesive layer covering the exposed surface of the metal bump.

Therefore, according to a conductive bump structure of the circuit boardand a method for fabricating the same provided in the present invention,an insulating layer and a resist layer with openings are formed on asurface of a circuit board, wherein the openings are corresponding toelectrical connection pads, so that the electrical connection pads areexposed. Then a conductive layer is formed on the surfaces of theopenings and resist layer. This thereby allows the conductive layer withlarger surface area to provide a sufficiently large area for subsequentelectroplating process and form a metal layer thereon by electroplating.Later, the metal layer and the conductive layer formed on a surface ofthe resist layer are removed, so as to reduce the difficulty ofelectroplating increased due to minimal area for electroplating.Further, the metal layer is filled in the openings of the insulatingprotective layer and the resist layer in order to flatten the surface ofthe metal layer; and then a portion of the metal layer is removed toform the metal bumps of even height, so as to avoid problems likeforming uneven height of conductive bumps on the surface of circuitboard, which is incurred as a result of directly forming the metal bumpsin the openings of the insulating protective layer and the resist layerby electroplating and will have a serious impact on the reliability ofthe electrical connecting process of circuit boards and externalelectronic components (including semiconductor chips).

Moreover, in accordance with a conductive bump structure of the circuitboard and a method for fabricating the same provided in the presentinvention, the conductive layer is formed on surfaces of the electricalconnection pads first, and then the metal layer is formed on theconductive layer of larger surface area via electroplating. Accordingly,the metal layer formed on the electrical connection pads via copperelectroplating, having a low material cost and faster electroplatingspeed, is made with copper characteristics to save the fabrication time.Further, the difficulty of electroplating is reduced because of having alarger surface area of the conductive layer for electroplating. As aresult, the conductive bump structure of the circuit provided in thepresent invention could reduce the amount of solder material used andthus reduce the cost of production. Meanwhile, the present inventioncould also avoid problems such as bridging effect and short circuit,resulting from using too much solder materials in the conventionalsolder reflow process; and hence provide the fine-pitch electricalconnection pads and solve problems caused by the conventional stencilprinting technique, such as size limitation on conductive bumps,restrictiosn on distances between contact pads or increase of productioncost and complexity of fabrication.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading thefollowing detailed description of the preferred embodiments, withreference made to the accompanying drawings, wherein:

FIG. 1A (PRIOR ART) is a cross-sectional schematic diagram of aconventional flip-chip component;

FIG. 2A (PRIOR ART) is a cross-sectional schematic diagram of aconventional circuit board having solder material deposited onelectrical connection pads via stencil printing technology;

FIGS. 3A to 3D (PRIOR ART) are cross-sectional schematic diagrams of aconventional pre-soldering bump of the circuit board in prior-art;

FIGS. 4A to 4I are cross-sectional schematic diagrams of a conductivebump structure of the circuit board in accordance with a first exemplaryembodiment of the present invention;

FIGS. 5A to 5G are cross-sectional schematic diagrams of a conductivebump structure of the circuit board in accordance with a secondexemplary embodiment of the present invention; and

FIGS. 6A to 6G are cross-sectional schematic diagrams of a conductivebump structure of the circuit board in accordance with a third exemplaryembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention relates generally to conductive bump structures ofcircuit boards and methods for fabricating the same, and moreparticularly, to a conductive bump structure formed on an electricalconnection pad of a circuit board for electrically connecting thecircuit board to the external electronic component. The followingdescription is presented to enable one of ordinary skill in the art tomake and use the invention and is provided in the context of a patentapplication and its requirements. Various modifications to the preferredembodiments and the generic principles and features described hereinwill be readily apparent to those skilled in the art. Thus, the presentinvention is not intended to be limited to the embodiments shown, but isto be accorded the widest scope consistent with the principles andfeatures described herein.

Proposed in the present invention can be more fully understood byreading the detailed description of the preferred embodiments. Whatneeds to be concerned here is that the drawings are simplified schematicdiagrams, and thus only constructs relevant to the present invention areillustrated.

FIGS. 4A-4I show a preferred embodiment of a conductive bump structureof a circuit board of the present invention and the method of making thesame.

Referring to FIG. 4A-4C, a surface of a circuit board formed with aplurality of electrical connection pads is provided first. Thefabrication of forming an electrical connection pad on a surface of acircuit board is further described as follows. As shown in FIG. 4A, aconductive layer 42 is formed on an insulating layer 41, which is formedon a surface of the circuit board, and a resist layer 43 is formed onthe conductive layer 42, wherein a plurality of openings 430 are formedin the resist layer 43. In one embodiment, the conductive layer 42 mayserve as an electrical conductive pathway for electroplating metalmaterials employed in subsequent processes, and be made of metals,multi-deposited metal layers, or any conductive molecule material suchas conductive polymer, polyacetylene, polyaniline, organosulfur ororganosulfide polymer and the like. The resist layer 43 may be aphoto-resist layer such as a dry film photo-resist or a liquidphoto-resist layer. The resist layer 43 is applied to the surface of theconductive layer 42 by performing process such as printing,spin-coating, laminating, adhering or the like. Then exposure anddeveloping is preformed for patterning the resist layer 43, so thatopenings 430 are formed in the resist layer 43 to expose a portion ofthe conductive layer 42 of the surface of the circuit board.

As shown in FIG. 4B, an electroplating process is preformed. During theelectroplating process, the conductive layer 42 served as an electricalconductive pathway, for example, a current transmission pathway, allowsthe electrical connection pads 410 to be formed in the openings 430 ofthe resist layer 43 via electroplating. Further, conductive wirings mayalso be formed on the surface of the circuit board simultaneously viaelectroplating (not shown). As shown in FIG. 4C, the resist layer andthe conductive layer 42 covered by the resist layer 43 are removed.

As shown in FIG. 4D, an insulating protective layer 45 is formed on thecircuit board comprising the electrical connection pads 410, and then aresist layer 46 is formed on the insulating protective layer 45. In theembodiment, the insulating protective layer 45 and the resist layer 46are formed on the surface of the circuit board in sequence by performingat least one of printing, coating, spin-coating, laminating, andadhering processes. The insulating protective layer 45 may be a masklayer and the resist layer 46 may be a photo-resist layer such as dryfilm photo-resist or liquid photo-resist, or a non-photosensitive layer

Referring to FIG. 4E, openings 450, 460 are formed on the insulatingprotective layer 45 and the resist layer 46 at positions correspondingto the electrical connection pads 410 to expose the electricalconnection pads 410. Further, the openings 450, 460 may be formed byplasma etching or laser etching.

Referring to FIG. 4F, a conductive layer 47 is formed on surfaces of theresist layer 46 and the openings 450, 460. The conductive layer 47serves as an electrical conductive pathway for electroplating metalmaterials in subsequent processes, and may be made of metals, alloys,stacked metal layers, or any conductive molecule material such asconductive polymers.

Referring to FIG. 4G, an electroplating process is performed. Theconductive layer 47 served as an electrical conductive pathway, providesa large surface area for electroplating. A metal layer 48 is thus formedon the conductive layer 47 via electroplating, wherein the openings 450,460 of the insulating protective layer 45 and the resist layer 46 arefilled with the metal layer 48. Further, the metal layer 48 may be madeof metals such as lead (Pb), tin (Sn), silver (Ag), copper (Cu), ortheir alloys. However, based on the implementation experience, the metallayer 48 is preferably made of, but not limit to, copper viaelectroplating, because the copper is a well-known electroplatingmaterial with a lower material cost.

Referring to FIG. 4H, a thinning process is performed to remove theconductive layer 47 and the metal layer 48 formed on the surface of theresist layer 46. Thus, the parts of the metal layer 48 and theconductive layer 47 formed at the position corresponding to theelectrical connection pad 410 and filled in the opening 450 of theinsulating protective layer and the opening 460 of the resist layer areretained, in order to form metal bumps 480 comprising the metal layer 48and the conductive layer 47 at even height. The thinning process mayinclude, but not limited to, etching or abrading process.

Referring to FIG. 4I, the resist layer 46 is moved by chemical meanssuch as etching or physical means such as tearing, and an adhesive layer49 is formed on the exposed surfaces of the metal bump 480. Further, thematerial of the adhesive layer 49 may be selected from, but not limitedto, at least one of the group consisting of copper (Cu), tin (Sn), lead(Pb), silver (Ag), nickel (Ni), gold (Au), platinum (Pt), their alloys,solder materials, and an organic solderability preservative (OSP), so asto form the conductive bumps 480 for electrically connecting the circuitboard to a semiconductor chip of an electronic devices.

Referring to the aforementioned fabricating methods, a conductive bumpstructure of the circuit board fabricated in accordance with presentinvention is provided, wherein a surface of the circuit board is formedwith an electrical connection pad 410 and covered by an insulatingprotective layer 45, an opening 450 is formed in the insulatingprotective layer 45 to expose the electrical connection pad 410 coveredby the insulating protective layer 45 and the conductive bump structureis formed on the electrical connection pad 410 of the circuit board andprotruded from the opening 450 of the insulating protective layer.Further, the conductive bump structure comprises a metal bump 480 havinga metal layer 48 and a conductive layer 47 formed on the lateral andbottom sides of the metal layer 48, wherein the metal bump 48 isprotruded from the opening of the insulating layer 41; and an adhesivelayer 49 covering the exposed surface of the metal bump 480.

Therefore, in one embodiment, according to a conductive bump structureof the circuit board and a method for fabricating the same provided inthe present invention, an insulating layer 45 and a resist layer 46 withopenings 450, 460 are formed on a surface of the circuit board, whereinthe openings 450, 460 are formed at positions corresponding toelectrical connection pads 410, so that the electrical connection pads410 are exposed. Then a conductive layer 47 is formed on the surfaces ofthe openings 450, 460 and resist layer 46. This thereby allows theconductive layer 47 with larger surface area to provide a sufficientlylarge area for subsequent electroplating process and form a metal layer48 on the conductive layer 47 by electroplating. Later, portions of themetal layer 48 and the conductive layer 47 formed on a surface of theresist layer 46 are removed, so as to reduce the difficulty ofelectroplating increased due to minimal area for electroplating.Further, the metal layer 48 is filled in the openings 450, 460, andportions of the metal layer 48 and conductive layer 47 are removed toform the metal bumps 480 of even height, so as to avoid problems likeforming uneven height of conductive bumps on the surface of circuitboard, which is incurred as a result of directly forming the metal bumpsin the openings of the insulating protective layer and the resist layerby electroplating and will have a serious impact on the reliability ofthe electrical connecting process of circuit boards and the externalelectronic component.

Moreover, in accordance with a conductive bump structure of the circuitboard and a method for fabricating the same provided in the presentinvention, the conductive layer 47 is formed on surfaces of theelectrical connection pads 410 first, and then the metal layer 48 isformed on the conductive layer 47 of larger surface area viaelectroplating. Accordingly, the metal layer 48 formed on the electricalconnection pads 410 via copper electroplating, having a low materialcost and faster electroplating speed, is made with coppercharacteristics. Further, portions of the metal layer 48 and conductivelayer 47 are removed to form the metal bumps 480, so as to save thefabrication time. Since a larger surface area of the conductive layer 47is provided for electroplating, the difficulty of electroplating is thusreduced.

Moreover, the adhesive layer 49 made of solder materials, which is highmaterial cost, is formed on the surfaces of the metal bumps 480, so asto reduce the usage of high cost solder materials to reduce the cost ofproduction. Such adhesive layer 49 also provides strong binding forcebetween the circuit board and the external device. Meanwhile, thepresent invention could also avoid problems such as bridging effect andshort circuit, resulting from using too much solder materials in theconventional solder reflow process; and hence provide the fine-pitchelectrical connection pads and solve problems caused by the conventionalstencil printing technique, such as size limitation on conductive bumps,restrictiosn on distances between contact pads or increase of productioncost and complexity of fabrication.

FIG. 5A-5G are cross-sectional schematic diagrams of a second preferredembodiment of a conductive bump structure of the circuit board. Thefabrication method provided herewith is similar to the one disclosed inthe foregoing embodiment; however, in this embodiment, openings areformed in the insulating protective layer before the resist layer.Later, openings of the resist layer are formed at positionscorresponding to electrical connection pads for subsequentelectroplating process.

Referring to FIG. 5A, a circuit board 50 having a surface formed with aplurality of electrical connection pads 510 is provided.

Referring to FIG. 5B, the surface of the circuit board 50 is covered byan insulating protective layer 55, wherein the insulating protectivelayer 55 is formed with a plurality of openings 550, so that theelectrical connection pads 510 are exposed from the insulatingprotective layer 55.

Referring to FIG. 5C, a resist layer 56 is formed on the insulatingprotective layer 55, wherein openings 560 are formed on the resist layer56 at positions corresponding to the openings 550 of the insulatingprotective layer 55 via exposure and developing, so as to expose theelectrical connection pads 510 formed on the surface of the circuitboard 50.

Referring to FIG. 5D, a conductive layer 57 is formed on surfaces of theresist layer 56 and openings 550, 560.

Referring to FIG. 5E, an electroplating process is performed. Theconductive layer 57 serves as an electrical conductive pathway andprovides a large surface area for electroplating. Later, a metal layer58 is formed on the conductive layer 57 via electroplating, wherein themetal layer 58 is filled in the openings 550, 560 of the insulatingprotective layer 55 and resist layer 56.

Referring to FIG. 5F, a thinning process is performed to remove portionsof the conductive layer 57 and metal layer 58 formed on the surface ofthe resist layer 56. However, the conductive layer 57 and the metallayer 58 formed in the openings 550, 560 are retained, so as to formeven height of metal bumps 580 comprising portions of the metal layer 58and the conductive layer 57 on the electrical connection pads 510 of thecircuit board 50. What is more is that, in the embodiment, the metallayer 58 and the conductive layer 57 on the surface of the resist layer56 are removed via thinning, and the metal layer 58 and the conductivelayer 47 which are formed at a position corresponding to the electricalconnection pad 510 formed on the surface of the circuit board and filledin the openings 560,550 of the resist layer and the insulatingprotective layer are retained, in order to form the metal bumps 580 ofeven height on the electrical connection pads 510 to provide a flatsurface for forming subsequent electrical connection with the externaldevice. Further, the thinning process may be, but not limited to,etching or abrading process.

Referring to FIG. 5G, subsequently, the resist layer 56 is moved bychemical means such as etching or physical means such as tearing, so asto form an adhesive layer 59 on the exposed surface areas of the metalbump 580.

FIG. 6A-6G are cross-sectional schematic views of a third preferredembodiment of conductive bump structures of a circuit board. Thefabrication method provided herewith is similar to the one disclosed inthe second embodiment; however, in this embodiment, a resist layer, ametal layer and a conductive layer formed on a surface of the resistlayer are removed at once, so as to form the conductive bumps on theelectrical connection pads of the circuit board.

Referring to FIG. 6A, a circuit board 60 having a surface formed with aplurality of electrical connection pads 610 is provided.

Referring to FIG. 6B, the surface of the circuit board 60 is covered byan insulating protective layer 62, wherein the insulating protectivelayer 62 is formed with a plurality of openings 630 to expose theelectrical connection pads 610 of the circuit board 60.

Referring to FIG. 6C, a resist layer 63 is formed on the insulatingprotective layer 62, wherein openings 630 are formed in the resist layer63 at positions corresponding to the openings 620 of the insulatingprotective layer 62 via exposure and developing, so as to expose theelectrical connection pads 610 formed on the surface of the circuitboard 60.

Referring to FIG. 6D, a conductive layer 64 is formed on surfaces of theresist layer 63 and the openings 620, 630.

Referring to FIG. 6E, an electroplating process is performed. Theconductive layer 64 serves as an electrical conductive pathway andprovides a large surface area for electroplating. Later, a metal layer65 is thus formed on the conductive layer 64 via electroplating, whereinmetal layer 65 is filled in the openings 620, 630 of the insulatingprotective layer 62 and resist layer 63.

Referring to FIG. 6F, the resist layer 63 is moved by physical meanssuch as tearing. Due to the tearing force applied to the resist layer63, a stress concentration effect occurs around the openings 620 of theresist layer 63, and thereby allows the conductive layer 64 and metallayer 65 to be removed simultaneously along with the removal of theresist layer 63, so as to form metal bumps 650 with even height on theelectrical connection pads 610. Arrangement as such provides a fairlyflat surface for connecting the circuit boards to the externalelectronic components (including semiconductor chips) in subsequentprocess.

Referring to FIG. 6G, an adhesive layer 66 is formed over the metalbumps 650.

Therefore, according to a conductive bump structure of the circuit boardand a method for fabricating the same provided in the present invention,an insulating layer and a resist layer with openings are formed on asurface of a circuit board, wherein the openings are corresponding toelectrical connection pads, so that the electrical connection pads areexposed. Then a conductive layer is formed on the surfaces of theopenings and resist layer. This thereby allows the conductive layer withlarger surface area to provide a sufficiently large area for subsequentelectroplating process and form a metal layer thereon by electroplating.Later, the metal layer and the conductive layer formed on a surface ofthe resist layer are removed; however, the metal layer and theconductive layer formed in the openings are retained to form metal bumpson the electrical connection pads of the circuit board, so as to reducethe difficulty of electroplating increased due to minimal area forelectroplating. Further, the metal layer is filled in the openings ofthe insulating protective and the resist layer in order to flatten thesurface of the metal layer; and then a portion of the metal layer isremoved to form the metal bumps of even height, so as to avoid problemslike forming uneven height of conductive bumps on the surface of circuitboard, which is incurred as a result of directly forming the metal bumpsin the openings of the insulating protective layer and the resist layerby electroplating and will have a serious impact on the reliability ofthe electrical connecting process of circuit boards and externalelectronic components (including semiconductor chips).

Moreover, in accordance with a conductive bump structure of the circuitboard and a method for fabricating the same provided in the presentinvention, the conductive layer is formed on surfaces of the electricalconnection pads first, and then the metal layer is formed on theconductive layer of larger surface area via electroplating. Accordingly,the metal layer formed on the electrical connection pads via copperelectroplating, having a low material cost and faster electroplatingspeed, is made with copper characteristics to save the fabrication time.Further, the difficulty of electroplating is reduced because of having alarger surface area of the conductive layer for electroplating. As aresult, the conductive bump structure of the circuit provided in thepresent invention could reduce the amount of solder material used andthus reduce the cost of production. Meanwhile, the present inventioncould also avoid problems such as bridging effect and short circuit,resulting from using too much solder materials in the conventionalsolder reflow process; and hence provide the fine-pitch electricalconnection pads and solve problems caused by the conventional stencilprinting technique, such as size limitation on conductive bumps,restrictions on distances between contact pads or increase of productioncost and complexity of fabrication.

Although the present invention has been described in accordance with theembodiments shown, one of ordinary skill in the art will readilyrecognize that there could be variations to the embodiments and thosevariations would be within the spirit and scope of the presentinvention. Accordingly, many modifications may be made by one ofordinary skill in the art without departing from the spirit and scope ofthe appended claims.

1. A method for fabricating a conductive bump structure of a circuitboard, comprising the steps of: providing the circuit board having atleast a surface formed with a plurality of electrical connection pads;forming an insulating protective layer and a resist layer on the circuitboard in sequence; forming a plurality of openings in the insulatingprotective layer and resist layer at positions corresponding to theelectrical connection pads to expose the electrical connection pads ofthe circuit board; forming a conductive layer on surfaces of the resistlayer and openings; forming a metal layer on the conductive layer viaelectroplating, and filling the metal layer in the openings of theinsulating protective layer and the resist layer; removing the metallayer and conductive layer formed on the surface of the resist layer viathinning, and retaining the metal layer and conductive layer filled inthe openings to form metal bumps on the electrical connection pads; andremoving the resist layer, and forming an adhesive layer over exposedsurfaces of the metal bumps, so as to form the conductive bump structurefor electrically connecting the circuit board to the external electroniccomponent.
 2. The method for fabricating a conductive bump structure ofa circuit board of claim 1, wherein the method for fabricating theelectrical connection pads comprises steps of: forming a conductivelayer on an insulating layer formed on a surface of the circuit board;forming a resist layer on the conductive layer, and forming openings ofthe resist layer to expose a portion of the conductive layer; andforming the electrical connection pads in the openings of the resistlayer via electroplating.
 3. The method for fabricating a conductivebump structure of a circuit board of claim 2, further comprising thestep of removing the resist layer and the conductive layer covered bythe resist layer.
 4. The method for fabricating a conductive bumpstructure of a circuit board of claim 1, wherein the openings of theinsulating protective layer and resist layer are formed via one ofplasma etching and laser drilling.
 5. The method for fabricating aconductive bump structure of a circuit board of claim 1, wherein themetal bumps are made of the metal layer and the conductive layer formedat positions corresponding to the electrical connection pads.
 6. Themethod for fabricating a conductive bump structure of a circuit board ofclaim 1, wherein the adhesive layer is an organic solderabilitypreservative.
 7. The method for fabricating a conductive bump structureof a circuit board of claim 1, wherein the adhesive layer is made of amaterial selected from the group consisting of copper (Cu), tin (Sn),lead (Pb), silver (Ag), nickel (Ni), gold (Au), platinum (Pt) and theiralloys.
 8. The method for fabricating a conductive bump structure of acircuit board of claim 1, wherein the metal layer is made of a materialselected from the group consisting of copper (Cu), tin (Sn), lead (Pb),silver (Ag), and their alloys.
 9. The method for fabricating aconductive bump structure of a circuit board of claim 1, wherein thethinning process is one of etching or abrading.
 10. The method forfabricating a conductive bump structure of a circuit board of claim 1,wherein the resist layer is removed via one of chemical stripping andphysical tearing.
 11. A method for fabricating a conductive bumpstructure of a circuit board, comprising the steps of: providing thecircuit board having at least a surface formed with a plurality ofelectrical connection pads; forming an insulating protective layer onthe circuit board in sequence, and forming a plurality of openings inthe insulating protective layer to expose the electrical connection padsof the circuit board; forming a resist layer on the insulatingprotective layer, and forming a plurality of openings in the resistlayer at positions corresponding to the openings of the insulatingprotective layer to expose the electrical connection pads; forming aconductive layer on exposed surfaces of the resist layer and openings;forming a metal layer on the conductive layer via electroplating, andfilling the metal layer in the openings; removing the resist layer, theconductive layer and metal layer formed on the surface of the resistlayer to form metal bumps on the electrical connection pads of thecircuit board, wherein the metal bumps comprise the metal layer andconductive layer; and forming an adhesive layer over exposed surfaces ofthe metal bumps.
 12. The method for fabricating a conductive bumpstructure of a circuit board of claim 11, wherein the method forfabricating the electrical connection pads comprises steps of: forming aconductive layer on an insulating layer formed on a surface of thecircuit board; forming a resist layer on the conductive layer, andforming openings of the resist layer to expose a portion of theconductive layer; and forming the electrical connection pads in theopenings of the resist layer via electroplating.
 13. The method forfabricating a conductive bump structure of a circuit board of claim 12,further comprising the step of removing the resist layer and theconductive layer covered by the resist layer.
 14. The method forfabricating a conductive bump structure of a circuit board of claim 11,wherein the process of removing the resist layer and conductive layercovered by the resist layer is to remove the metal layer and conductivelayer formed on the surface of the resist layer first via thinning andretain the metal layer and conductive layer filled in the openings. 15.The method for fabricating a conductive bump structure of a circuitboard of claim 11, wherein the process of removing the resist layer andconductive layer covered by the resist layer is to remove the resistlayer, the metal layer and conductive layer formed on the surface of theresist layer first via physical methods.
 16. The method for fabricatinga conductive bump structure of a circuit board of claim 11, wherein theadhesive layer is made of a material selected from the group consistingof copper (Cu), tin (Sn), lead (Pb), silver (Ag), nickel (Ni), gold(Au), platinum (Pt) and their alloys.
 17. The method for fabricating aconductive bump structure of a circuit board of claim 11, wherein theadhesive layer is an organic solderability preservative.
 18. The methodfor fabricating a conductive bump structure of a circuit board of claim11, wherein the metal layer is made of a material selected from thegroup consisting of copper (Cu), tin (Sn), lead (Pb), silver (Ag), andtheir alloys.
 19. The method for fabricating a conductive bump structureof a circuit board of claim 11, wherein the openings of the insulatingprotective layer and the resist layer are formed by patterning processsuch as exposure and developing or by laser.
 20. A conductive bumpstructure of a circuit board, wherein a surface of the circuit board isformed with an electrical connection pad and covered by an insulatingprotective layer, an opening is formed in the insulating protectivelayer to expose the electrical connection pad covered by the insulatingprotective layer and the conductive bump structure is formed on theelectrical connection pad of the circuit board and protruded from theopening of the insulating protective layer, the conductive bumpstructure comprising: a metal bump having a metal layer and a conductivelayer formed on the lateral and bottom sides of the metal layer, whereinthe metal bump is protruded from the opening of the insulating layer;and an adhesive layer covering the exposed surface of the metal bump.21. The conductive bump structure of a circuit board of claim 20,wherein the adhesive layer is made of a material selected from the groupconsisting of copper (Cu), tin (Sn), lead (Pb), silver (Ag), nickel(Ni), gold (Au), platinum (Pt) and their alloys.
 22. The conductive bumpstructure of a circuit board of claim 20, wherein the adhesive layer isan organic solderability preservative.